Alphawave, a chip supplier and designer, this month teamed up with Keysight, a manufacturer of test and verification equipment, to demonstrate the compatibility of its controller PCIe 6.0 and a physical interface to Keysight test equipment with data rates of 64 GT/s. The move confirms that Alphawave is ready to build PCIe 6.0 chips, joining a growing list of companies that are preparing the ecosystem for the first commercially available PCIe 6.0 devices in 2024.
Synopsys has been offering its PCIe 6.0 IP package containing the controller and physical interface (PHY) since 2021, and earlier this year the company demonstrated compatibility of its PCIe Gen6 solution with Intel’s test chip.
Alphawave’s PCIe 6.0 64 GT/s semiconductor implementation not only runs the Keysight protocol probe at full speed with four-signaling pulse amplitude modulation (PAM4), but also supports the CXL 2.0 protocol, which is an industry first. The implementation also fully supports PCIe Gen6 forward error correction (FEC), FLIT mode, and other features of the new interconnect standard. Additionally, this PCIe Gen6 platform can be further expanded using the CXL 3.0.
“Test and measurement are critical aspects of interoperability, allowing Alphawave Semi to bring our products and solutions to market faster for customers,” said Letizia Giuliano, vice president of IP Product Marketing at Alphawave Semi. “We are excited about our collaboration with Keysight, which accelerates the journey to 64 GT/s with Keysight’s state-of-the-art PCIe 6.0 protocol verification solution and instills confidence in our ability to consistently deliver connectivity solutions that accelerate AI processing in high-performance computing and data infrastructure.”
Synopsys licenses its intellectual property and technology primarily to large chip designers. Alphawave, by contrast, designs custom chips or licenses technology to smaller companies that are not inclined to develop or implement intellectual property themselves. The company says its PCIe subsystem is extremely power efficient, offers low latency, and “was built on top of the industry’s most successful PAM4 SerDes IP.” Additionally, this PCIe Gen6 platform can be further expanded with the CXL 3.0 protocol.
2023-12-28 17:54:48
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