PCI Express 6.0 technology released. Twice the speed against PCIe 5.0, already 8 GB / s per line

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As soon as PCI Express 5.0 got into computers, it is already on the horizon PCIe 6.0. This new version has now been officially released and will deliver twice the speed thanks to the PAM4 signal you know from GDDR6X. For example, an M.2 SSD for PCIe 6.0 × 4 will be able to read or write up to 32 GB / s.

If you monitor your hardware regularly, you probably know that after PCI Express 5.0which is already on the market in Intel Alder Lake processors, there have been major changes in this technology connecting peripherals, GPUs and SSDs with chipsets and processors. And you are finally here: PCI Express 6.0 is the biggest change in this standard since the beginning. However, it does not bring the optics, as previously expected, but the PAM4 signaling, with which it reaches twice the speed still on copper.

PCI Express doubles each generation. Until recently, the most widespread PCI Express 3.0 had a speed per line of 1 GB / s (so for example an SSD for PCIe 3.0 × 4 had a theoretical speed limit of 4 GB / s). Today, the new hardware already has PCIe 4.0 at 2 GB / s per line, and PCIe 5.0 at Alder Lake processors gives 4 GB / s per line. PCI Express 6.0, which has now been completed and its specifications officially released for hardware manufacturers, doubles the speed of these interfaces, so we get 8 GB / s per line, 8x faster than PCI Express 3.0.

The PCI Express 6.0 × 16 slot for a GPU or similar demanding accelerator will therefore have a throughput of 256 GB / s. An SSD for an M.2 slot with 6.0 × 4 PCIe connectivity will be able to whistle at sequential read or write speeds of up to 32 GB / s (in reality, this will be a bit less due to overhead). This data is for speed in one direction, but the interface also supports the same fast communication in the opposite direction, it is duplex.

PAM4 signaling: big change for PCI Express

However, the implementation of this acceleration was more difficult this time. While versions 4.0 and 5.0 increased the real “frequency” of communication on the line, PCI Express 6.0 switches from classic NRZ encoding, which transmits zero or one in one pulse, to PAM4 encoding, ie pulse-amplitude modulation. In this pulse, each pulse has four different signal levels, so two bits can be transmitted in it – the four levels can distinguish the values ​​00, 01, 10 and 11. Because there is twice as much data in each pulse, PAM4 encoding can double the data throughput on the line at the same pulse frequency.

The use of PAM4 has the advantage that the computer industry leans towards it in other interfaces as well. This means that there will be “synergies” with other technologies in developing and improving the efficiency and performance of PHY – high-speed Ethernet, or memory (PAM4 is the first to use GDDR6X).

More: GeForce RTX 3000 has new GDDR6X memories with a speed of up to 21 GHz, they use PAM4

It also has disadvantages. PAM4 signal processing is more difficult because instead of “off / on”, not only the on but also the signal level must be distinguished at once. Controllers and PHYs that support PCIe 6.0 and PAM4 can take up more space on chips, so they can also make silicon a little more expensive. And they will probably often have higher consumption. But it is said to increase less than speed, so energy efficiency can probably improve if we calculate it as the watts consumed needed for a certain throughput. Communication on a × 16 slot, for example, could consume more with PCIe 6.0 than with PCIe 5.0 × 16. But if, for example, PCIe 5.0 × 16 were replaced by PCIe 6.0 × 8 with the same throughput, efficiency and consumption could be better.

Doubling the speed would be much more difficult with copper conductors without this enhancer – it was even previously considered that PCIe would switch to optics, which would logically be a big complication. However, PAM4 suffices with roughly the same signal frequency. The wires only need to be able to keep the interference low enough to safely distinguish the four signal levels. It’s like an MLC record for an SSD (NAND memory) as opposed to an SLC record.

Because the PAM4 signal will be more susceptible to noise, interference, and errors, it will need more robust error correction, which the authors of the PCI-SIG focused on when developing PCI Express. A new Forward Error Correction (FEC) and CRC will be used to correct signal errors, but their design should not increase latency. This required setting a fixed flow control unit (“Flit”) of 256 bytes, which requires the FEC algorithm. But packets can then have a variable length. This method of communication will automatically be used in PCIe 6.0 mode.

Compatibility maintained

Although the type of signaling has been significantly changed in this way, even PCI Epxress 6.0 will maintain a good habit when the new technology is compatible with the previous one. Devices for older versions of PCIe will therefore be able to be used in a slot that supports PCI Express 6.0. Conversely, if you need a PCIe 6.0 SSD, it will be possible to install it in the slot of an older board with a lower version of PCIe. In these cases, the highest speed supported by the slower side is always used. PCI Express 6.0 mode and its new method of communication can only be set up between the device and the host if, during initialization, they verify that both parties can use the new technology.

Thus, PCI Express 6.0 will continue the long-term compatibility of components on the PC platform (and other devices that use PCI Express) and will not carry out any radical revolutions.

When will it be on computers?

New PCI Express technologies always come ahead of time before they come into practice, because once the specification is finalized and it takes time, everything needs to be fine-tuned on the devices being developed to verify that the controllers are working really reliably. Technology release announcements such as today’s therefore precede the actual availability of hardware. According to PCI-SIG, it should probably take 12-18 months for PCI Express 6.0 to appear in the very first real hardware.

However, the timing will vary from one manufacturer to another, depending on how they pursue, how these dates align with their development cycles, or how willing they are to invest in adding aid. Therefore, we can’t guess much yet when PCI Express 6.0 will appear on Intel or AMD processors (and boards for them), or when an SSD for this interface will appear. For orientation: from the release of PCI Express 5.0 to the launch of Alder Lake processors with PCIe 6.0, it took 30 months, from PCI Express 4.0 to Ryzeny 3000 (the first processors for PCs with support) it was only 21 months.

We do not yet have information on any specific generation of processors or any of the companies in which support for PCI Express 6.0 is already planned. However, if we take a conservative estimate of two to three years, then PCI Express 6.0 could bring processors released in 2024 or 2025. So it’s quite a long way off, and the coming years will still be marked by PCIe 5.0.

Sources: PCI-SIG (1, 2, 3, 4)