Presentation at the ‘Advanced Semiconductor Package Conference’ hosted by THE ELEC
Accelerate the development of advanced packaging technologies such as fan-out and 3D
“Preparing to apply a new method for next-generation fan-out packaging”
Samsung Electronics introduces a new method to strengthen its ‘Fan-Out (FO)’ packaging technology. In order to respond to the increasing adoption of high-tech semiconductors such as HBM (High Bandwidth Memory), it plans to apply a new packaging method that can increase the degree of substrate integration compared to the existing ones in the future.
Lee Chung-seon, team leader of Samsung Electronics, made this announcement about the next-generation packaging technology roadmap at the ‘2023 Advanced Semiconductor Package Innovation Process Conference’ hosted by THE ELEC at COEX, Seoul on the 12th.
At the end of last year, Samsung Electronics established an AVP business team dedicated to advanced packaging and has been focusing on developing related technologies. Currently, the advanced packaging fields that Samsung Electronics is focusing on are two areas: small chip packaging such as fan-out (FO) and 3D, and large chip packaging such as 2.5D and 3.5D.
Among them, fan-out is a technology that removes input/output (I/O) terminal wiring from the chip. More I/O terminals can be placed outside, and electrical performance and thermal efficiency can be improved by reducing the wiring length between the semiconductor and the main board. Samsung Electronics has applied FO-WLP, which performs packaging at the wafer level, and FO-PLP, which proceeds packaging with rectangular panels, to its development and mass production processes.
However, the challenges it faces are also formidable. In order for fan-out packaging to respond to next-generation memories such as HBM, the circuit spacing of the board (PCB) must be further reduced. HBM is a semiconductor that connects several DRAMs vertically, and its high bandwidth allows data to be transmitted faster.
Lee Choong-seon, team leader, said, “Currently, the SAP method can realize circuit spacing of up to 2/2 micrometers” and added, “If the HBM technology becomes more sophisticated, the spacing should be reduced to 1/1 micrometer or less. There are limits,” he said. The SAP method is a method of coating a part of the substrate except for the circuit, plating the circuit, and then removing the coating again.
Accordingly, Samsung Electronics plans to introduce the Damascene method in the future as an alternative to the SAP method. Damascene is a method of forming grooves in circuit parts and forming circuits through electroplating (a technique of coating a thin metal film on the surface through current).
Lee Chung-seon, team leader, added, “To implement the next-generation fan-out packaging, we have a direction to apply the damascene method in earnest.”
Meanwhile, the ‘2023 Advanced Semiconductor Package Innovation Process Conference’ is an event co-hosted by THE ELEC, a media specializing in electronic parts, and Y ELEC, an electronic parts knowledge channel. It was prepared to point out the current status of advanced package materials and process technologies, which are increasingly important in the semiconductor industry. Major companies in the packaging field participated, including Samsung Electronics, SK Hynix, Stats Chippack Korea, Amco Technology Korea, LG Chem, Naeil Technology, Henkel, MK Electronics, TSE, Terraon, and Cadence Korea.
Packaging is a post-processing technology that cuts and packages processed wafers into chips. As the front-end process technology that refines the line width of the circuit is gradually reaching its limit, the industry has developed advanced packaging technology that can improve semiconductor performance and efficiency instead of the front-end process. In particular, heat dissipation that effectively removes heat generated from chips and heat-resistance technology that can maintain chip performance even at high temperatures are emerging as major topics.
The Elec = Reporter Jang Kyung-yoon [email protected]
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