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Intel Lakefield
This year, AMD will also provide us with processors with Zen 3 cores, whose chipsets will be layered and will carry in one layer the same hardware as the in-line Zen 3 and in the other additional L3 cache or V-Cache (SRAM). These are already much more powerful chips than Lakefield, but cooling should also not be a problem, as the V-Cache is located where the original cache on the chiplet is connected to the V-Cache also via TSV. And because the V-Cache sits in the middle and does not interfere with the edges of the chiplet, where the processor cores make up the main portion of the waste heat, cooling should not be a problem.
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It can be said that they used a very similar procedure to the IME as AMD, which turned the chiplet upside down from its original position, so that it could directly connect the V-Cache chip to it, while the side parts were supplemented by ” structural silicon “, or simply a plain piece of silicon. To this end, it was of course also necessary to manufacture / modify all parts so that their combined thickness corresponded to the original chiplet.
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In the picture from IME we see something similar, but in four layers, which is called the connection “Face-to-Face and Back-to-Back”. The first and second layers are thus oriented “faces” towards each other, as well as the third and fourth.
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Only after the fitting and joining of all layers was the creation of vertical TSVs, ie a conical hole with a diameter of up to about 13 μm was basically punched into the layered chips, which were then filled with copper.
But we will not learn much about how well such an assembly of four layers can be cooled. After all, it is for such chips that it also develops TSMC a special equivalent of “intrachip” water cooling, where the water block will be part of the chip itself, ie the cooling medium will flow directly through it.
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Prices of related products:
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