Home » today » Business » Abstract of TSMC technical highlights!Grasp new developments in hybrid junction, CFET, and silicon photonics on the similar time

Abstract of TSMC technical highlights!Grasp new developments in hybrid junction, CFET, and silicon photonics on the similar time

TSMC held a know-how discussion board on the twenty third. On this regard, this newspaper has additionally organized the details of this discussion board to permit readers to right away perceive the newest progress of TSMC.

This text will introduce so as:

  • Superior process-related applied sciences: N3 household / N2 course of / NanoFlex / A16 / Tremendous Rail / CFET
  • Superior Packaging Associated Applied sciences: SoW / 3DFabric / SoIC (& Hybrid Connectivity) / CoWoS / InFo
  • Particular process-related applied sciences: silicon photonics

Superior course of

N3 a household

N3E entered mass manufacturing within the fourth quarter of final yr As for N3P, which is prepared for mass manufacturing within the second half of this yr, product efficiency is near that of N3E, and buyer product design has been accomplished (tape. -out). TSMC identified that as a result of N3P has higher efficiency, energy consumption, and space (PPA), most 3-nanometer merchandise use N3P course of know-how.

By way of manufacturing capability, because of the demand for HPC and cell phones, TSMC’s 3nm manufacturing capability this yr has greater than tripled in comparison with final yr.

N2 Course of

The N2 course of makes use of nanosheet transistors to offer higher vitality effectivity. At present, 2-nanometer know-how is progressing easily.

Sooner or later, extra N2 households will seem, together with N2P, N2X and different purposes.


TSMC’s N2 know-how will likely be paired with NanoFlex to realize new advances in collaborative optimization of design know-how. NanoFlex gives chip designers with 2nm versatile customary elements, that are the fundamentals of chip design, decrease peak elements save house and have increased energy consumption effectivity.

Prior to now, it was troublesome to combine elements of various heights into designs Nevertheless, TSMC’s newest know-how will help prospects to optimize the mix of excessive and low elements in the identical design block, which might enhance the pace by 15%, thus bettering the ability consumption, efficiency and the applying space (PPA) to get one of the best stability.


A16 know-how will use the subsequent technology nanosheet know-how along with Tremendous Energy Rail structure and is anticipated to be produced within the second half of 2026. Completely different wires will likely be used this time, which TSMC believes is one of the best answer for high-performance computing (HPC) merchandise.

In comparison with the N2P course of, the A16 makes use of an excellent rail rising the computing pace by 8~10% on the similar Vdd (operation voltage). modified to this point +1.10 Euro.

tremendous tram

Because the variety of chip stacks will increase, energy provide turns into more and more problematic, because it should move by 10 to twenty stack layers to offer energy and knowledge indicators to the transistors under. , and the circuit layer structure through which interconnection strains and energy strains coexist. gradual has additionally been an issue.

TSMC’s “Tremendous Rail” strikes the ability provide community to the again of the wafer, liberating up extra kind issue house for sign networks on the entrance of the wafer, rising logic density and efficiency, bettering energy dissipation, and decreasing to massive IR voltage drop. TSMC additionally stated that this know-how is the primary within the business and that it maintains the pliability of gate density and part width.


Transistor structure has advanced from planer to FinFET after which to nanosheet structure One of many subsequent processes is the “complementary area impact transistor” (CFET), which is a direct stacking of nFET and pFET.

This know-how stacks completely different supplies comparable to silicon (Si) and germanium (Ge) from prime to backside to deliver p-type and n-type area impact transistors nearer collectively. By way of this superposition technique, CFET eliminates the n to p separation bottleneck and reduces the cell’s energetic space by 2 occasions.

TSMC indicated that this know-how can considerably enhance part circulate and enhance CFET density by 1.5 to 2 occasions. At present, TSMC has efficiently demonstrated that nFETs and pFETs will be positioned on wafers on transistors.

Zhang Xiaoqiang additionally shared the CFET construction that TSMC’s lab efficiently made at ISSCC 2024 prior to now, he stated, “It is a actual built-in half made within the lab. You may see how lovely the curve is (backside left image. ).

Superior packaging

SoW(system degree integration know-how)

SoW makes use of TSMC’s InFO and CoWoS packaging know-how to combine the logic die and HBM reminiscence utilizing the complete wafer. TSMC hopes to not solely enhance chip degree, but additionally enhance efficiency, pace and different features by system degree.

At present, system degree wafers utilizing InFO know-how have been put into mass manufacturing. . It’s focused to be used within the AI ​​and HPC fields to broaden the computing capabilities required for next-generation knowledge facilities.

3 Material

TSMC’s 3DFabric know-how household contains three major platforms: SoIC, CoWoS, and InFO, together with 2D and 3D front-end and back-end interconnect applied sciences.


The SoIC platform is used for 3D silicon wafer stacking and gives two stacking options: SoIC-P (Bumped) and SoIC-X (Bumpless). SoIC-P is a micro chip stack answer for cost-effective purposes comparable to cell purposes.

One other SoIC-X answer makes use of Hybrid Bonding, appropriate for HPC and AI interface areas), bringing interconnection density to a brand new degree.

Zhang Xiaoqiang identified that TSMC’s present Bonding Bonding (Bond pitch) hybrid bond density can attain 6 microns, and might attain 2-3 microns sooner or later, it advances Micron Bump know-how, which is at the moment increased than 30 microns The purpose sooner or later is to cut back it to 12 microns.

TSMC revealed that it’s at the moment seeing a gradual enhance in buyer demand for SoIC-X know-how, with 30 buyer designs anticipated to be finalized by the tip of 2026.


CoWoS contains CoWoS-S, CoWoS-L and CoWoS-R The associated fee is especially primarily based on completely different interface supplies. The CoWoS-S interposer makes use of silicon, CoWoS-L makes use of LSI (native silicon interconnect), and the CoWoS-R interface makes use of RDL wiring to attach the small dies .

Relying on product necessities, SoIC chips will be related to CoWoS or InFO. At present, AMD’s MI300A / MI300 X is the primary to undertake SoIC-X and CoWoS know-how.

The Blackwell AI accelerator launched by TSMC and Nvidia makes use of CoWoS-L know-how to combine 2 SoCs utilizing a 5nm course of and eight HBM stacks in a single module.

As well as, TSMC’s CoWoS know-how can combine superior SoC/SoIC with HBM to fulfill the strict necessities of AI chips available on the market. TSMC is at the moment mass-producing SoIC and despatched by CoWoS-S, and plans to develop a SoIC chip with 8 occasions the masks dimension (adopting the A16 course of) and a CoWoS answer with 12 stacks excessive bandwidth reminiscence (center within the determine under). ) (under), mass manufacturing is anticipated to start in 2027.

Silicon photonics

Zhang Xiaoqiang identified that silicon photons primarily have two elements, one is the photonic half, comparable to optical waveguide, which doesn’t want a really excessive course of, and a 65-nanometer course of is sufficient; To transform electro-optical gentle, electrical energy should be It’s getting quicker and quicker, so superior processes 7nm and even 5nm are wanted.

For the silicon photonics format, TSMC is growing COUPE (Compact Common Photonic Engine), which stacks digital dies (EICs) on photonic dies (PICs) by 3D SoIC-X stacking know-how to cut back energy consumption additionally after degradation to be stacked. In comparison with conventional stacking, this method permits decrease resistance on the die-to-die interface and better vitality effectivity.

It’s value noting that high-speed RF radio frequency indicators will be achieved by a hybrid copper-to-copper (Cu-Cu) SoIC-X connector.

Zhang Xiaoqiang defined that the COUPE (photon engine) will likely be related to the pc chip (Compute Die) sooner or later, and a number of cables will likely be wanted to attach it, so 3D stacking know-how is essential.

TSMC plans to finish COUPE certification of the small plug-in connector in 2025 and combine the CoWoS packaging substrate of the co-packaged optical component (CPO) in 2026, making the change EIC / PIC / closely built-in on the packaging degree. , which helps Scale back energy consumption 2 occasions and scale back latency by 10 occasions.

As well as, TSMC additionally plans to combine COUPE into the CoWoS intermediate layer, thus decreasing energy consumption by one other 5 occasions and latency by 2 occasions. At current, COUPE merchandise are primarily appropriate for HPC areas or knowledge facilities.

(Unique picture supply: TSMC)

Additional studying:

2024-05-24 06:04:45
#Abstract #TSMC #technical #highlightsMaster #developments #hybrid #junction #CFET #silicon #photonics #time

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