Building ENIAC: How a Neurodivergent Teacher and Students Recreated Computing History for Its 80th Anniversary

When a Robotics Teacher’s ENIAC Replica Exposes the Gaps in Modern Compute Pedagogy

Tom Burick’s full-scale cardboard-and-hot-glue ENIAC replica at PS Academy Arizona isn’t just a STEM fair project—it’s a quiet indictment of how we teach computational fundamentals in the age of AI abstractions. Built by neurodivergent students using 300 square meters of cardboard, 1,600 hot-glue sticks, and 18,000 simulated vacuum tubes, the machine mirrors the original 1945 ENIAC’s architecture: 40 panels in a U-shape, 20 accumulators, and function tables storing constants via physical switches. Even as the original ENIAC executed 5,000 operations per second—a thousandfold speedup over electromechanical contemporaries—this replica runs at 0 FLOPS. Its value lies not in throughput but in forcing students to confront the physicality of computation: tracing data paths through plugboards, manually setting constants via rotary switches, and debugging timing errors introduced by hand-wired signal propagation delays. In an era where LLMs generate kernel modules and NPUs hide tensor math behind Python decorators, Burick’s project raises a critical question: Are we producing developers who can optimize L3 cache misses but can’t explain how a flip-flop stores state?

The Tech TL;DR:

• Burick’s ENIAC replica uses zero active components—18,000 LEDs simulate tube glow via 555 timer circuits driven by a single Arduino Mega, consuming <5W total.
• Students reported 40% improvement in understanding von Neumann bottlenecks after physical interaction with the replica’s bus contention limitations (per internal PS Academy assessment, Q1 2026).
• The project’s open-source documentation (CC-BY-SA 4.0) is hosted on GitHub, enabling schools to replicate the build for under $200 in materials.

The core problem this addresses is the growing disconnect between high-level AI frameworks and the hardware realities that constrain them. Modern CS curricula emphasize PyTorch training loops while ignoring how memory bandwidth limits transformer inference latency—a gap that becomes critical when deploying LLMs on edge devices. Burick’s replica makes tangible the very constraints that cause real-world production issues: when students physically reroute cables to avoid signal reflection on the replica’s backplane, they internalize why PCIe 5.0 x16 slots matter for GPU clusters or why NVMe-over-Fabrics reduces storage tail latency. This isn’t nostalgia; it’s applied computer architecture pedagogy. As one embedded systems CTO noted after reviewing the project’s schematics,

“We hire graduates who can fine-tune LoRA adapters but stare blankly when asked to calculate the setup time for a 74LS175 latch. Projects like this bridge the chasm between AI theory and silicon reality.”

— Elena Rodriguez, CTO, embedded systems consultants specializing in automotive AI.

Funding transparency is essential here: Burick received no corporate sponsorship. Materials were sourced via DonorsChoose crowdfunding ($1,200 raised) and school budget allocations. The replica’s design files—including panel schematics, switch constants mappings, and Arduino firmware for tube simulation—are maintained under PS Academy Arizona’s GitHub repository, updated quarterly by student interns. This stands in stark contrast to vaporware “AI education platforms” that lock curriculum behind SaaS paywalls while delivering superficial engagement metrics. The primary technical source guiding the build was the original 1946 ENIAC technical manual (University of Pennsylvania Moore School archives), cross-referenced with the Smithsonian’s restored panel measurements to ensure dimensional accuracy within 2mm tolerance.

Implementation-wise, the replica’s “vacuum tubes” consist of diffused LEDs driven by 555 timer astable multivibrators, programmed via Arduino to mimic tube ionization delay (approximately 100ns simulated via software debouncing). Below is the core timing loop used to simulate asynchronous tube operation—a deliberate departure from cycle-accurate FPGA approaches to emphasize pedagogical transparency over performance:

// ENIAC tube simulation - PS Academy Arizona v2.1 // Simulates 100ns tube delay via blocking delay (not for production use!) #define TUBE_DELAY_US 100 // Simulated microsecond delay per tube pulse void simulateTube(int tubePin) { digitalWrite(tubePin, HIGH); delayMicroseconds(TUBE_DELAY_US); // Blocks CPU - illustrates synchronous bottleneck digitalWrite(tubePin, LOW); delayMicroseconds(TUBE_DELAY_US); } void loop() { for(int i = 2; i <= 22; i+=2) { // Simulate accumulator panel tubes simulateTube(i); } // Function table constant lookup would go here } 

This blocking design choice is pedagogically genius: it forces students to confront why ENIAC’s accumulators couldn’t operate in parallel without precise clock synchronization—a lesson directly applicable to debugging race conditions in modern CUDA kernels or managing memory coherence in multi-socket Xeon systems. When a student’s wire jumper introduced 2ns of excess capacitance (measured via oscilloscope during build), causing tube simulation jitter, it became a live lesson in signal integrity—far more memorable than any SPICE simulation.

The directory bridge writes itself: educational institutions deploying similar hands-on compute history projects increasingly require IT infrastructure auditors to validate electrical safety of student-built systems (particularly when scaling to higher voltages) and special education curriculum developers to adapt neurodivergent-friendly pedagogies—like Burick’s use of hyperfocus-friendly repetitive tasks (wiring identical accumulator panels) and spatial reasoning leveraging—to scale such programs district-wide. One Arizona district CIO confirmed after visiting PS Academy:

“We’re piloting a modified ENIAC build next semester specifically for our 2e (twice-exceptional) learners. The tactile feedback loop reduces anxiety while building concrete mental models of data flow—something no Jupyter notebook can replicate.”

As enterprise AI stacks grow increasingly opaque—with TPU v5e pods abstracted behind Kubernetes operators and LLM serving layers hiding quantization artifacts—projects like this remind us that true systems thinking begins not with framework upgrades but with wire strippers and a multimeter. The trajectory isn’t toward more abstraction, but toward deliberate re-grounding: the next wave of effective infrastructure engineers will be those who can oscillate between Python decorators and electron flow diagrams with equal fluency. For schools seeking to implement this model, the GitHub repo provides a BOM, build guide, and lesson plans aligned to CSTA K-12 standards—no Series B funding required.