With the release of the Apple iPhone 12, iPhone 12 Pro and the iPad Air (2020), consumers around the world are experiencing a 5nm chipset for the first time. Apple’s A14 Bionic SoC, made by TSMC, has a whopping 11.8 billion transistors in one processor. A lot, even if you compare that to the 8.5 billion transistors of its predecessor, the A13 Bionic. But the manufacturers are already looking further.
Apple isn’t the only tech company to use 5nm chips. For example, Huawei uses the 5nm Kirin 9000 for its smartphone top models and 5G network base stations (until the US trade department put a stop to this). Next year, Samsung will also reportedly come with two 5nm Exynos chips, while Qualcomm will join the club with the Snapdragon 875.
Apple currently uses a 7nm chip from Qualcomm for its 5G connections, but it will also go to 5nm in the next generation. In all likelihood, we can expect faster iPhones again next year. Because manufacturers are already working on the next generation of chips.
TSMC and ASML are looking forward to 3nm and 2nm chips
The 5nm chipset is now the cream of the crop, and faster, better and more energy efficient than its predecessors. But companies like TSMC, ASML and Samsung don’t have the time to pat themselves on the back about their 5nm components. That’s because they are already working on the next generation of chips, which work with a 3nm process. In 1965, Intel co-founder noted, Gordon Moore, note that the transistor density on a chip doubled every year. He later revised that to double the transistor density every two years. So there is little time left to celebrate the 5nm milestone.
One of the tools developed to keep Moore’s Law alive is extreme ultraviolet (EUV) lithography. Lithography is used to print circuits on thin silicon slices. When you think about the size of a chip and the billions of transistors that have to be placed on it, you will understand that extremely thin markings have to be made in a chip. EUV uses ultraviolet rays to make this possible. The N5 node that TSMC works with can use 5nm for up to 14 layers. The 3nm node process could provide a 15% speed increase with the same number of transistors as 5nm and use up to 30% less power (at the same clock speeds and complexity).
The Dutch lithography company ASML says that lithography at 3nm can be used on more than 20 layers. Peter Wennink, the company’s CEO, says:
With the N5 we can handle more than 10 layers. In N3 there will be more than 20 and we really see an upward trend here. The advantage of this is that we can then switch to single cartridges and no longer need DUV (deep ultraviolet) technology with double cartridges. This does not only apply to processors, but also to DRAM.
Single and double cartridges
When a single lithographic exposure does not produce a print with a sufficiently sharp resolution, exposures with double patterning are used. This process is also used by memory chip manufacturers (RAM and NAND). That sharpness is a hurdle that must be overcome when going towards 2nm. Because you can imagine that double patterns also need more space than single patterns.
TSMC plans to use FinFET transistors one more time for its 3nm process before switching to GAAFET (gate all around) on 2nm chips. Unlike FinFET, which does not surround a channel on all sides, GAA surrounds a channel with a gate. The latter method makes the leakage current almost negligible.
US trade war with China
Wennink says the company must follow U.S. Department of Commerce rules when it comes to shipping lithography systems to China. This means that Chinese chip makers, if it is up to the American government, will not yet be able to use Dutch techniques to make chips at 5nm, let alone at 3 and 2nm. TSMC is a Taiwanese company and can therefore use the very latest techniques.