Summary of SK Hynix’s Split-Cell Flash Technology
This text details a new approach to NAND flash memory developed by SK hynix, called multi-site cell technology or split-cell flash. Here’s a breakdown of the key points:
* The Problem: Traditional PLC (planar cell layer) NAND flash struggles with voltage crowding as it tries to store 32 voltage states in a single cell. This leads to slower speeds, reduced endurance, and potential data errors.
* The Solution: Split-cell flash divides a single NAND cell into two independent half-cells.
* How it effectively works:
* Each half-cell stores 6 voltage states, combining to represent a 5-bit value.
* The half-cells operate in parallel, similar to RAID-0, but combining voltage states during access instead of striping data.
* The cell shape is elliptical to accommodate an insulating wall and separate bit line connections.
* Benefits:
* Reduced Voltage crowding: Wider voltage gaps in each half-cell minimize electron leakage.
* Faster Speeds: Simultaneous reading of both halves leads to faster read speeds.
* Improved Endurance: Lower voltage stress reduces wear and tear on the cells.
* Shorter Programming Time: Reduced electron leakage contributes to faster programming.
* Challenges:
* Increased Complexity & Cost: Requires additional semiconductor process steps (cell division, gap filling).
* Manufacturability: SK Hynix is still evaluating the feasibility of mass production.
* Current Status: SK hynix has demonstrated working wafers, proving the concept is viable beyond simulations.
In essence, split-cell flash aims to overcome the limitations of high-density NAND by distributing the voltage state burden across two smaller, more manageable cells, resulting in a more efficient and reliable storage solution.
