CXMT to Leapfrog Samsung with 4F² DDR5 RDIMM by 2026, wccftech.com reports

CXMT Readies DDR5 RDIMM on 4F² Architecture to Target Samsung Roadmap

ChangXin Memory Technologies (CXMT) is preparing to introduce a DDR5 Registered Dual In-Line Memory Module (RDIMM) using the 4F² memory cell architecture before the end of 2026, putting the Chinese chipmaker roughly two years ahead of Samsung's projected rollout, wccftech.com reported.

The Tech TL;DR:

• CXMT plans to launch a 4F²-based DDR5 RDIMM by the end of 2026, out-pacing Samsung’s 2028 target for the same architecture.
• The 4F² design stacks transistors and capacitors vertically, shrinking the cell footprint to a perfect square and boosting IC cell density by 30 to 50 percent.
• CXMT is also applying High-k Metal Gate (HKMG) technology and expanding production toward a projected capacity of 600,000 wafers per month.

The timeline emerged during a speech by CXMT President Dr. Cao Kanyu at the 4th Integrated Chip and Chiplet Conference in Shanghai, wccftech.com reported. Dr. Cao Kanyu outlined the company’s progress on the next-generation 4F² DRAM architecture and hybrid bonding techniques, declaring that the server-geared memory product will arrive ahead of industry competitors. Samsung reportedly intends to produce memory products on the 4F² architecture in 2028.

Architectural Mechanics of the 4F² Memory Cell Shift

The registered dual in-line memory module functions as a hardware buffer, holding incoming signals from the central processing unit for precisely one clock cycle before transmitting them to the memory chips. This process curtails electrical load, allowing server operators to install higher concentrations of high-capacity RAM sticks onto a single motherboard.

The shift to the 4F² process alters the underlying cell geometry. Traditional layouts place components horizontally, whereas the 4F² design stacks one transistor and one capacitor vertically. This configuration reduces the surface footprint of a single memory cell to a square measuring 4 times the minimum feature size squared ($4 times F^2$), comprising exactly two bitlines and two wordlines. Implementing this structure allows DRAM manufacturers to increase IC cell density by 30 to 50 percent.

CXMT first published research on the 4F² architecture in 2021. Transitioning from a 6F² to a 4F² architecture shrinks the memory cell area by roughly 33 percent at the same feature size, requiring new transistors. Industry observers note that CXMT’s initial deployment will likely utilize a partial derivative of the 4F² architecture on its new 15nm G5 DRAM process.

Integration of High-k Metal Gate Technology

To combat process miniaturization constraints, CXMT has adopted High-k Metal Gate (HKMG) technology, replacing traditional silicon-based insulators with materials such as hafnium oxide ($HfO_2$). This change suppresses current leakage and associated thermal waste while boosting power efficiency and operational speeds.

According to wccftech.com, CXMT is applying HKMG technology to its G4 DRAM fabrication process—believed to be on the 1z node—as well as LPDDR5X products. A social media post by Fred Chen on October 10, 2026, highlighted that CXMT initiated mass production of G5, utilizing Saxion Self-Aligned Quadruple Patterning (SAQP) as a core manufacturing step, with a subsequent transition to G6 anticipated prior to monolithic 3D DRAM.

Concurrently, CXMT is scaling manufacturing volume. The company operates three 300mm DRAM fabs, each with a capacity of approximately 100,000 wafers per month, totaling 300,000 wafers per month by the end of 2026. An additional HBM-focused capacity of roughly 50,000 wafers per month is slated for completion by late 2026. Construction of two new fabs in Shanghai and Hefei is expected to push total production capacity to 600,000 wafers per month, positioning CXMT to surpass Micron in volume production by 2030.

Samsung Fab Strategies and Wafer-to-Wafer Hybrid Bonding

In contrast to CXMT’s approach, Samsung plans to introduce the 4F² architecture through its B1b process—its first sub-10nm DRAM fabrication process, officially renamed D0a. Under Samsung’s methodology, memory cells and surrounding driver circuitry (the peri) will be fabricated on separate wafers and subsequently joined via wafer-to-wafer hybrid bonding, stacking the memory cells directly on top of the peri circuitry.

Because hybrid bonding involves high manufacturing costs, market analysts anticipate that Samsung will price its next-generation DRAM products at a significant premium.

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