KAIST Develops “Nano Sandpaper” for Atomic-Level Semiconductor Processing | Improves AI Chip Performance & Reduces Waste

by Rachel Kim – Technology Editor

A team of researchers at the Korea Advanced Institute of Science and Technology (KAIST) has developed a novel surface processing technique for semiconductors, dubbed “nano sandpaper,” that utilizes vertically aligned carbon nanotubes to achieve atomic-level precision. The breakthrough, announced February 11, 2026, promises to improve the performance and reliability of advanced semiconductors, including those used in artificial intelligence (AI) applications.

The research, led by Professor Sanha Kim of KAIST’s Department of Mechanical Engineering, addresses limitations in current semiconductor manufacturing processes. Traditional methods, such as chemical mechanical polishing (CMP), rely on chemical slurries and abrasive particles, generating substantial waste and requiring extensive cleaning. The nano sandpaper offers a potentially more environmentally friendly alternative.

“This is an original study demonstrating that the everyday concept of sandpaper can be extended to the nanoscale and applied to ultra-fine semiconductor manufacturing,” Professor Kim stated. “We hope this technology will lead not only to improved semiconductor performance but also to environmentally friendly manufacturing processes.”

The nano sandpaper consists of carbon nanotubes – thousands of times thinner than a human hair – fixed within a polyurethane matrix, with a portion of the nanotubes exposed on the surface. This structure prevents abrasive detachment, ensuring consistent performance and durability. According to the research team, the abrasive density of the nano sandpaper exceeds 1,000,000,000 grit, significantly surpassing that of commercially available sandpaper, which typically ranges from 40 to 3000 grit.

Experimental results demonstrated the effectiveness of the technology. Rough copper surfaces were polished to nanometer-level smoothness, and in tests involving semiconductor pattern planarization, the nano sandpaper reduced “dishing defects” – indentations in the interconnect lines that can compromise performance – by up to 67% compared to conventional CMP processes.

The research team anticipates applications for the nano sandpaper in advanced semiconductor planarization processes, particularly for high-bandwidth memory (HBM) used in AI servers, and in hybrid bonding, a next-generation semiconductor interconnection technology.

Dr. Sukkyung Kang, a Ph.D. Candidate under the supervision of Professor Kim at the Advanced Manufacturing and Surface Engineering (AMSE) Laboratory, served as the first author of the study, which was published online January 8, 2026, in the journal Advanced Composites and Hybrid Materials (IF 21.8). Dr. Kang recently received the Gold Prize in the Mechanical Engineering division at the 31st Samsung Human Tech Paper Award for this work.

The research was supported by funding from the National Research Foundation of Korea, the Ministry of Science and ICT, and KAIST’s internal research programs.

You may also like

Leave a Comment

This site uses Akismet to reduce spam. Learn how your comment data is processed.