The Tech TL;DR:

• The Hardware: Nvidia’s Vera CPU combines 88 custom Olympus cores, an LPDDR5X memory subsystem, and second-generation Scalable Coherent Fabric.
• The Benchmark: Early production testing with Cadence Jasper and Synopsys VCS shows up to a 1.5x performance boost on select EDA tasks.
• The Workflow Impact: Faster logic simulation and formal verification allow engineering teams to run more iterations and reduce downstream design flaws before tapeout.

Addressing Bottlenecks in Modern Silicon Verification

Modern semiconductor development requires years of validation, edge-case identification, and architectural iteration before a design ever reaches manufacturing. While GPUs and machine learning accelerators handle massive parallelism well, critical phases of EDA remain heavily dependent on high-performance CPU architecture. Logic simulation, formal verification, and digital implementation demand fast individual cores, predictable low-latency memory access, and high throughput across large regression compute farms.

The architecture pairs 88 custom Nvidia Olympus cores with an efficient LPDDR5X memory subsystem and a second-generation Scalable Coherent Fabric. This configuration is designed to deliver sustained per-core performance and low memory latency, metrics that directly dictate how quickly verification engineers can complete functional tests.

Early Benchmark Gains with Cadence and Synopsys

Initial production testing conducted by Nvidia highlights concrete performance gains across major EDA software packages. By optimizing runtime behavior for the Vera CPU architecture, engineers observed significant execution speedups on compute-heavy validation pipelines.

Cadence Jasper, a formal verification platform that leverages machine learning and smart proof technology to locate bugs early in the design cycle, was deployed alongside Synopsys VCS, a high-performance functional verification solution used to simulate complex logic prior to hardware fabrication.

Beyond initial benchmarking, Nvidia is continuing joint application profiling, software optimization, and system-level tuning with both tool vendors. These engineering efforts aim to expand performance margins across a wider array of register-transfer level (RTL) simulation workflows.

Integrating Vera into the Internal Development Pipeline

# Sample Slurm workload manager script for EDA regression testing
#!/bin/bash
#SBATCH --job-name=rtl_regression_vera
#SBATCH --nodes=4
#SBATCH --ntasks-per-node=88
#SBATCH --partition=compute-vera
#SBATCH --time=06:00:00

echo "Initializing EDA regression suite on Vera compute nodes..."
module load synopsys/vcs/2026.04 cadence/jasper/2026.03

# Execute distributed formal verification run
vcs -full64 -sverilog -debug_acc+all -f run_list.f -o simv
./simv +vcs+lic+wait

The Roadmap Toward Rosa and Continuous Feedback Loops

Nvidia’s deployment of Vera underscores a broader architectural strategy: pairing specialized processing units with the workloads they execute best. While GPUs and specialized AI accelerators handle parallel data processing algorithms, high-performance CPUs remain essential for serial logic simulation and formal verification tasks.

Looking past the current deployment cycle, Nvidia plans to scale its CPU roadmap further with the introduction of the next-generation Rosa CPU, which will feature the Nvidia Rigel core. By utilizing its own silicon design to build subsequent processor generations, the company is creating an internal feedback loop connecting software optimization, tool vendors, and advanced systems engineering.