Intel Nova Lake: No Vertical Cache, But Massive 144MB bLLC Explained
Intel is preparing a significant challenge to AMD’s dominance in gaming CPUs with its upcoming Nova Lake processors, potentially matching and even exceeding AMD’s 3D V-Cache technology. Recent leaks detail Intel’s approach, which eschews stacked cache in favor of a large on-die “bLLC” (backside Low-Latency Cache) implementation.
According to information shared by leaker HXL and reported by several tech publications, the Nova Lake Compute Tile, in a configuration of 8 Performance-cores (P-cores) and 16 Efficient-cores (E-cores), will come in two variants. One will have an area of approximately 110+ mm2, while the version incorporating the bLLC will measure 150+ mm2, both fabricated using TSMC’s N2 process. This 40 mm2 difference has sparked analysis regarding Intel’s strategy.
The key finding is that Intel is not pursuing a traditional stacked cache approach, like AMD’s 3D V-Cache. Instead, Intel appears to be integrating a substantial 144MB of L3 cache directly onto the Compute Tile via the bLLC. This contrasts with previous expectations of Intel adopting a similar vertical stacking method to AMD. The bLLC approach allows Intel to potentially achieve comparable cache capacity without the complexities and costs associated with stacking.
Analysis suggests Intel is expanding its existing L3 cache infrastructure rather than adding a separate cache die. The company has been progressively integrating the L3 cache closer to the core clusters with each successive architecture, starting with Rocket Lake and continuing through Lunar Lake and Panther Lake. This evolution culminated in a design where the L3 cache is interconnected with both P-cores and E-cores via a unified ring bus. Nova Lake builds on this foundation by further expanding the L3 cache within the Compute Tile itself.
Calculations based on TSMC N2 process characteristics indicate that the 40 mm2 area increase attributable to the bLLC translates to approximately 108MB of additional L3 cache, alongside necessary supporting logic. This would bring the total L3 cache for Nova Lake models with bLLC to 144MB, matching the potential capacity of AMD’s Zen 6 CPUs with dual 3D V-Cache dies, as reported in December 2025. Intel’s approach prioritizes efficiency and cost-effectiveness by leveraging existing infrastructure and avoiding the complexities of a separate cache stack.
The implications of this design choice are significant. Intel aims to deliver competitive gaming performance without incurring the substantial costs associated with stacked cache. The bLLC implementation is designed to be transparent to the operating system, providing increased cache capacity with minimal impact on latency or access times. Intel is reportedly segmenting its Nova Lake lineup, with higher-end models featuring the bLLC paired with more powerful GPUs, while more mainstream offerings will omit the bLLC to manage costs.
AMD is responding to this challenge. Leaks suggest AMD may increase the capacity of its Zen 6 3D V-Cache dies to 144MB each, potentially offering up to 288MB in dual-die configurations. However, the increased cache capacity comes with potential cost implications. The competitive landscape between Intel and AMD is intensifying, with both companies vying for the gaming performance crown. As of February 12, 2026, neither company has released official performance benchmarks for their upcoming CPUs.