AMD has patented an active bridge chiplet with a cache, what will it be for?

AMD has long used passive interposers, or silicon connections under all and whole chips that are interconnected by them. Intel has opted for a more economical EMIB, but both solutions have in common that they are only connections. However, if two (or more) chips are to be connected in this way, then why should the offered area of ​​the interposer not be used at least for additional memory. Logically, there is an L3 cache or simply LLC (Last Level Cache), which will serve all chips or chipsets that are connected to the interposer. But here we can talk specifically about the active bridge chiplet, or Active Bridge Chiplet.

The newly registered patent speaks specifically of GPU chipsets, and it is quite clear where the wind is blowing from. AMD in the new generation of Radeons uses an integrated Infinity Cache, which is based on the L3 cache of Zen processors and is part of the GPU itself. If Infinity Cache moved to the interposer, it could serve two or more GPU chipsets at the same time.

The Active Bridge Chiplet would essentially take on some of the I / O chip roles in Ryzen and EPYC processors, and this is an improvement patent registered in January this year, in which it was still a passive interconnection of GPU chipsets, where everyone would have their own part of LLC.

The question is how and when AMD will want to use such a thing. It is basically certain that chiplet graphics will come to the market in a few years by AMD, NVIDIA and Intel, and Intel is closest to that. However, they could first start in professional or data center products (Intel Ponte Vecchio) and also AMD could decide to use them first in products with CDNA architecture (Radeon Instinct) and not in gaming RDNA and as far as NVIDIA is concerned, in its case we are looking towards the Hopper generation (NVIDIA GH100), while before it comes Lovelace generation (or will be Hopper for data centers and Lovelace for regular graphics).

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However, this does not mean that Active Bridge Chiplets will be deployed in the first generation of chiplet GPUs, so we have to wait.

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