AMD has long used passive interposers, or silicon connections under all and whole chips that are interconnected by them. Intel has opted for a more economical EMIB, but both solutions have in common that they are only connections. However, if two (or more) chips are to be connected in this way, then why should the offered area of the interposer not be used at least for additional memory. Logically, there is an L3 cache or simply LLC (Last Level Cache), which will serve all chips or chipsets that are connected to the interposer. But here we can talk specifically about the active bridge chiplet, or Active Bridge Chiplet.
The newly registered patent speaks specifically of GPU chipsets, and it is quite clear where the wind is blowing from. AMD in the new generation of Radeons uses an integrated Infinity Cache, which is based on the L3 cache of Zen processors and is part of the GPU itself. If Infinity Cache moved to the interposer, it could serve two or more GPU chipsets at the same time.
However, this does not mean that Active Bridge Chiplets will be deployed in the first generation of chiplet GPUs, so we have to wait.
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